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| ZILOG PRELIMINARY Z89C00 16-BIT DIGITAL SIGNAL PROCESSOR PRELIMINARY PRODUCT SPECIFICATION Z89C00 16-BIT DIGITAL SIGNAL PROCESSOR FEATURES s s s s s s s s 16-Bit Single Cycle Instructions Zero Overhead Hardware Looping 16-Bit Data Ready Control for Slow Peripherals Single Cycle Multiply/Accumulate (100 ns) Six-Level Stack 512 Words of On-Chip RAM Static Single-Cycle Operation s s s s s s s 16-Bit I/O Port 4K Words of On-Chip Masked ROM Three Vectored Interrupts 64K Words of External Program Address Space Two Conditional Branch Inputs/Two User Outputs 24-Bit ALU, Accumulator and Shifter IBM(R) PC Development Tools GENERAL DESCRIPTION The Z89C00 is a second generation, 16-bit, fractional, two's complement CMOS Digital Signal Processor (DSP). Most instructions, including multiply and accumulate, are accomplished in a single clock cycle. The processor contains 1 Kbyte of on-chip data RAM (two blocks of 256 16-bit words), 4K words of program ROM and 64K words of program memory addressing capability. Also, the processor features a 24-bit ALU, a 16 x 16 multiplier, a 24-bit Accumulator and a shifter. Additionally, the processor contains a six-level stack, three vectored interrupts and two inputs for conditional program jumps. Each RAM block contains a set of three pointers which may be incremented or decremented automatically to affect hardware looping without software overhead. The data RAMs can be simultaneously addressed and loaded to the multiplier for a true single cycle multiply. There is a 16-bit address and a 16-bit data bus for external program memory and data, and a 16-bit I/O bus for transferring data. Additionally, there are two general purpose user inputs and two user outputs. Operation with slow peripherals is accomplished with a ready input pin. The clock may be stopped to conserve power. Development tools for the IBM PC include a relocatable assembler, a linker loader, and an ANSI-C compiler. Also, the development tools include a simulator/debugger, a cross assembler for the TMS320 family assembly code and a hardware emulator. To assist the user in understanding the Z89C00 DSP Q15 two's complement fractional multiplication, an application note has been included in this product specification as an appendix. Notes: All Signals with a preceding front slash, "/", are active Low, e.g., B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection Power Ground Circuit VCC GND Device VDD VSS DC 4083-00 1 2 External Program ROM PD15-PD0 16 PD 16 PC Register Pointer 0-2 256 Word RAM 0 256 Word RAM 1 Register Pointer 4-6 Instruction Register 16 EXT15-EXT0 16-Bit Bus Switch S-Bus X Y GENERAL DESCRIPTION (Continued) ZILOG PA15-PA0 16 PA /ROMEN 16 4K Word ROM Figure 1. Functional Block Diagram PRELIMINARY D-Bus 16-bit I/O Port Ready /RDYE 2 ER//W, /EI 3 EA2-EA0 16 x16 Multiplier 24-bit P 24 24-Bit Bus P-Bus Switch Stack 3 Interrupt INT2-INT0 /RESET MUX Shifter Status (5) User Port 2 UI1-UI0 2 UO1-UO0 B A ALU Z89C00 16-BIT DIGITAL SIGNAL PROCESSOR ACC DC 4083-00 ZILOG PRELIMINARY Z89C00 16-BIT DIGITAL SIGNAL PROCESSOR EXT 15 EXT13 EXT 10 EXT 11 EXT14 EXT12 EXT9 EXT8 EXT7 EXT6 EXT5 EXT3 EXT2 EXT4 EXT1 9 VSS PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 UO1 UO0 INT2 INT1 INT0 UI1 UI0 HALT /ROMEN CLK /RES /RDYE ER//W /EI EA2 EA1 EA0 Z89C00 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 PA11 PA12 PA13 PA14 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 Figure 2. 68-Pin PLCC Pin Assignments DC 4083-00 PA15 VDD EXT0 52 51 50 49 48 47 46 45 44 VSS 3 ZILOG PRELIMINARY Table 1. 68-Pin PLCC Pin Identification No. 1-9 10 11-26 27-38 39 40-43 44-46 47 48 49 50 51 52 53 54-55 56-58 59-60 61-64 65 66-68 Symbol EXT15-EXT7 VSS PD15-PD0 PA11-PA0 VDD PA15-PA12 EA2-EA0 /EI ER//W /RDYE /RES CLK /ROMEN HALT UI1-UI0 INT2-INT1 UO1-UO0 EXT3-EXT0 VSS EXT6-EXT4 Function External data bus Ground Program data bus Program address bus Power Supply Program address bus External address bus R/W for external bus External bus direction Data ready Reset Clock Enable ROM Stop execution User inputs Interrupts User outputs External data bus Ground External data bus Z89C00 16-BIT DIGITAL SIGNAL PROCESSOR Direction Input/Output Input Input Output Input Output Output Output Output Input Input Input Input Input Input Input Output Input/Output Input Input/Output PIN FUNCTIONS CLK Clock (input). External clock. The clock may be stopped to reduce power. EXT15-EXT0 External Data Bus (input/output). Data bus for user defined outside registers such as an ADC or DAC. The pins are normally in output mode except when the outside registers are specified as source registers in the instructions. All the control signals exist to allow a read or a write through this bus. ER//W External Bus Direction (output, active Low). Data direction signal for EXT-Bus. Data is available from the CPU on EXT15-EXT0 when this signal is Low. EXT-Bus is in input mode (high-impedance) when this signal is High. EA2-EA0 External Address (output). User-defined register address output. One of eight user-defined external registers is selected by the processor with these address pins for read or write operations. Since the addresses are part of the processor memory map, the processor is simply executing internal reads and writes. /EI Enable Input (output). Write timing signal for EXT-Bus. Data is read by the external peripheral on the rising edge of /EI. Data is read by the processor on the rising edge of CLK, not /EI. HALT Halt State (input). Stop Execution Control. The CPU continuously executes NOPs and the program counter remains at the same value when this pin is held High. This signal must be synchronized with CLK. INT2-INT0 Three Interrupts (rising edge triggered). Interrupt request 2-0. Interrupts are generated on the rising edge of the input signal. Interrupt vectors for the interrupt service starting address are stored in the program memory locations 0FFFH for INT0, 0FFEH for INT1 and 0FFDH for INT2. Priority is: 2 = lowest, 0 = highest. PA15-PA0 Program memory address bus (output). For up to 64K x 16 external program memory. These lines are tristated during Reset Low. 4 DC 4083-00 ZILOG PRELIMINARY Z89C00 16-BIT DIGITAL SIGNAL PROCESSOR PD15-PD0 Program Memory Data Input (input). Instructions or data are read from the address specified by PD15PD0, through these pins and are executed or stored. /RES Reset (input, active Low). Asynchronous reset signal. A Low level on this pin generates an internal reset signal. The /RES signal must be kept Low for at least one clock cycle. The CPU pushes the contents of the PC onto the stack and then fetches a new Program Counter (PC) value from program memory address 0FFCH after the Reset signal is released. RES Low tri-states the PA and PD bases. /ROMEN ROM Enable (input). An active Low signal enables the internal ROM. Program execution begins at 0000H from the ROM. An active High input disables the ROM and external fetches occur from address 0000H. /RDYE Data Ready (input). User-supplied Data Ready signal for data to and from external data bus. This pin stretches the /EI and ER//W lines and maintains data on the address bus and data bus. The ready signal is sampled from the rising edge of the clock with appropriate setup and hold times. The normal write cycle will continue from the next rising clock only if ready is active. UI1-UI0 Two Input Pins (input). General purpose input pins. These input pins are directly tested by the conditional branch instructions. These are asynchronous input signals that have no special clock synchronization requirements. UO1-UO0 Two Output Pins (output). General purpose output pins. These pins reflect the inverted value of status register bits S5 and S6. These bits may be used to output data by writing to the status register. ADDRESS SPACE Program Memory. Programs of up to 4K words can be masked into internal ROM. Four locations are dedicated to the vector address for the three interrupts (0FFDH-0FFFH) and the starting address following a Reset (0FFCH). Internal ROM is mapped from 0000H to 0FFFH, and the highest location for program is 0FFBH. If the /ROMEN pin is held High, the internal ROM is inactive and the processor executes external fetches from 0000H to FFFFH. In this case, locations FFFC-FFFF are used for vector addresses. Internal Data RAM. The Z89C00 has an internal 512 x 16-bit word data RAM organized as two banks of 256 x 16-bit words each, referred to as RAM0 and RAM1. Each data RAM bank is addressed by three pointers, referred to as Pn:0 (n = 0-2) for RAM0 and Pn:1 (n = 0-2) for RAM1. The RAM addresses for RAM0 and RAM1 are arranged from 0-255 and 256-511, respectively. The address pointers, which may be written to or read from, are 8-bit registers connected to the lower byte of the internal 16-bit D-Bus and are used to perform no overhead looping. Three addressing modes are available to access the Data RAM: register indirect, direct addressing, and short form direct. These modes are discussed in detail later. The contents of the RAM can be read or written in one machine cycle per word without disturbing any internal registers or status other than the RAM address pointer used for each RAM. The contents of each RAM can be loaded simultaneously into the X and Y inputs of the multiplier. Registers. The Z89C00 has 12 internal registers and up to an additional eight external registers. The external registers are user definable for peripherals such as A/D or D/A or to DMA or other addressing peripherals. External registers are accessed in one machine cycle the same as internal registers. DC 4083-00 5 ZILOG PRELIMINARY Z89C00 16-BIT DIGITAL SIGNAL PROCESSOR FUNCTIONAL DESCRIPTION General. The Z89C00 is a high-performance Digital Signal Processor with a modified Harvard-type architecture with separate program and data memory. The design has been optimized for processing power and minimizing silicon space. Instruction Timing. Many instructions are executed in one machine cycle. Long immediate instructions and Jump or Call instructions are executed in two machine cycles. When the program memory is referenced in internal RAM indirect mode, it takes three machine cycles. In addition, one more machine cycle is required if the PC is selected as the destination of a data transfer instruction. This only happens in the case of a register indirect branch instruction. An Acc + P => Acc; a(i) * b(j) P calculation and modification of the RAM pointers, is done in one machine cycle. Both operands, a(i) and b(j), can be located in two independent RAM (0 and 1) addresses. Multiply/Accumulate. The multiplier can perform a 16-bit x 16-bit multiply or multiply accumulate in one machine cycle using the Accumulator and/or both the X and Y inputs. The multiplier produces a 32-bit result, however, only the 24 most significant bits are saved for the next instruction or accumulation. The multiplier provides a flow through operation whenever the X or Y register is updated, an automatic multiply operation is performed and the P register is updated. For operations on very small numbers where the least significant bits are important, the data should first be scaled by eight bits (or the multiplier and multiplicand by four bits each) to avoid truncation errors. Note that all inputs to the multiplier should be fractional two's complement 16-bit binary numbers. This puts them in the range [-1 to 0.9999695], and the result is in 24-bits so that the range is [-1 to 0.9999999]. In addition, if 8000H is loaded into both X and Y registers, the resulting multiplication is considered an illegal operation as an overflow would result. Positive one cannot be represented in fractional notation, and the multiplier will actually yield the result 8000H x 8000H = 8000H (-1 x -1 = -1). ALU. The 24-bit ALU has two input ports, one of which is connected to the output of the 24-bit Accumulator. The other input is connected to the 24-bit P-Bus, the upper 16 bits of which are connected to the 16-bit D-Bus. A shifter between the P-Bus and the ALU input port can shift the data by three bits right, one bit right, one bit left or no shift. Hardware Stack. A six-level hardware stack is connected to the D-Bus to hold subroutine return addresses or data. The CALL instruction pushes PC+2 onto the stack. The RET instruction pops the contents of the stack to the PC. User Inputs. The Z89C00 has two inputs, UI0 and UI1, which may be used by jump and call instructions. The jump or call tests one of these pins and if appropriate, jumps to a new location. Otherwise, the instruction behaves like a NOP. These inputs are also connected to the status register bits S10 and S11 which may be read by the appropriate instruction (Figure 3). User Outputs. The status register bits S5 and S6 connect through an inverter to UO0 and UO1 pins and may be written to by the appropriate instruction. Interrupts. The Z89C00 has three positive edge triggered interrupt inputs. An interrupt is acknowledged at the end of any instruction execution. It takes two machine cycles to enter an interrupt instruction sequence. The PC is pushed onto the stack. A RET instruction transfers the contents of the stack to the PC and decrements the stack pointer by one word. The priority of the interrupts is 0 = highest, 2 = lowest. Registers. The Z89C00 has 12 physical internal registers and up to eight user-defined external registers. The EA2EA0 determines the address of the external registers. The /EI, /RDYE, and ER//W signals are used to read or write from the external registers. 6 DC 4083-00 ZILOG PRELIMINARY Z89C00 16-BIT DIGITAL SIGNAL PROCESSOR REGISTERS There are 12 internal registers which are defined below: Register P X Y A SR Pn:b PC Register Definition Output of Multiplier, 24-bit, Read Only X Multiplier Input, 16-bit Y Multiplier Input, 16-bit Accumulator, 24-bit Status Register, 16-bit Six Ram Address Pointers, 8-bit Each Program Counter, 16-bit Pn:b are the pointer registers for accessing data RAM. (n = 0,1,2 refer to the pointer number) (b = 0,1 refers to RAM bank 0 or 1). They can be directly read from or written to, and can point to locations in data RAM or indirectly to Program Memory. EXT(n) are external registers (n = 0 to 7). There are eight 16-bit registers here for accessing External data, peripherals, or memory. Note that the actual register RAM does not exist on the chip, but would exist as part of the external device such as an ADC result latch. BUS is a read-only register which, when accessed, returns the contents of the D-Bus. The following are virtual registers as physical RAM does not exist on the chip. Register EXTn BUS Dn:b Register Definition External registers, 16-bit D-Bus Eight Data Pointers Dn:b refer to possible locations in RAM that can be used as a pointer to locations in program memory. The programmer decides which location to choose from two bits in the status register and two bits in the operand. Thus, only the lower 16 possible locations in RAM can be specified. At any one time there are eight usable pointers, four per bank, and the four pointers are in consecutive locations in RAM. For example, if S3/S4 = 01 in the status register, then D0:0/D1:0/D2:0/D3:0 refer to locations 4/5/6/7 in RAM bank 0. Note that when the data pointers are being written to, a number is actually being loaded to Data RAM, so they can be used as a limited method for writing to RAM. P holds the result of multiplications and is read only. X and Y are two 16-bit input registers for the multiplier. These registers can be utilized as temporary registers when the multiplier is not being used. The contents of the P register will change if X or Y is changed. A is a 24-bit Accumulator. The output of the ALU is sent to this register. When 16-bit data is transferred into this register, it goes into the 16 MSB's and the least significant eight bits are set to zero. Only the upper 16 bits are transferred to the destination register when the Accumulator is selected as a source register in transfer instructions. DC 4083-00 7 ZILOG PRELIMINARY Z89C00 16-BIT DIGITAL SIGNAL PROCESSOR REGISTERS (Continued) N S15 OV S14 Z C UI1 S11 UI0 S10 SH3 S9 OP S8 IE S7 UO1 UO0 S6 S5 S4 S3 S2 RPL S1 S0 Ram Pointer 000 001 010 011 100 101 110 111 "Short Form Direct" bits User Output 0-1 Interrupt Enable Overflow protection Read and Write Loop Size 256 2 4 8 16 32 64 128 S13 S12 MPY output shifted right by 3 bit with sign extension User Input 0-1 Carry Read Only Zero Overflow Negative Figure 3. Status Register SR is the status register (Figure 3) which contains the ALU status and certain control bits as shown in the following table. Status Register Bit S15 (N) S14 (OV) S13 (Z) S12 (L) S11 (UI1) S10 (UI0) S9 (SH3) S8 (OP) S7 (IE) S6 (UO1) S5 (UO0) S4-3 S2-0 (RPL) RPL Description S2 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 Loop Size 256 2 4 8 16 32 64 128 Function ALU Negative ALU Overflow ALU Zero Carry User Input 1 User Input 0 MPY Output Shifted Right by Three Bits Overflow Protection Interrupt Enable User Output 1 User Output 0 "Short Form Direct" Bits RAM Pointer Loop Size The status register may always be read in its entirety. S15-S10 are set/reset by the hardware and can only be read by software. S9-S0 can be written by software. 8 DC 4083-00 ZILOG PRELIMINARY Z89C00 16-BIT DIGITAL SIGNAL PROCESSOR S15-S12 are set/reset by the ALU after an operation. S11-S10 are set/reset by the user inputs. S6-S0 are control bits described elsewhere. S7 enables interrupts. S8, if 0 (reset), allows the hardware to overflow. If S8 is set, the hardware clamps at maximum positive or negative values instead of overflowing. If S9 is set and a multiply instruction is used, the shifter shifts the result three bits right with sign extension. PC is the Program Counter. When this register is assigned as a destination register, one NOP machine cycle is added automatically to adjust the pipeline timing. RAM ADDRESSING The address of the RAM is specified in one of three ways (Figure 4): RAM0 RAM Pointers P0:0 P1:0 P2:0 %37 @P1:0 %37 %0321 256 x 16-Bit %FF RAM1 %FF RAM Pointers P0:1 256 x 16-Bit P1:1 P2:1 %0321 %04 S4 / S3 = 01 %00 %00 Data Pointers Internal ROM %1000 D0:0 D1:0 D2:0 4K x 16-Bit D3:0 %0321 D0:1 D1:1 D2:1 D3:1 @@P1:0 %0321 %1234 @D0:1 The following Instructions load %1234 into the Accumulator: LD A,@@P1:0 LD A,@D0:1 %0000 Figure 4. RAM, ROM, and Pointer Architecture 1. Register Indirect Pn:b n = 0-2, b = 0-1 The most commonly used method is a register indirect addressing method, where the RAM address is specified by one of the three RAM address pointers (n) for each bank (b). Each source/destination field in Figures 5 and 8 may be used by an indirect instruction to specify a register pointer and its modification after execution of the instruction. b D8 D3 D2 n1 D1 n0 D0 RAM Pointer Register Operation RAM Bank Figure 5. Indirect Register DC 4083-00 9 ZILOG PRELIMINARY Z89C00 16-BIT DIGITAL SIGNAL PROCESSOR RAM ADDRESSING (Continued) The register pointer is specified by the first and second bits in the source/destination field and the modification is specified by the third and fourth bits according to the following table: D3-D0 00xx 01xx 10xx 11xx xx00 xx01 xx10 xx11 NOP +1 -1/LOOP +1/LOOP P0:0 or P0:1 P1:0 or P1:1 P2:0 or P2:1 Meaning No Operation Simple Increment Decrement Modulo the Loop Count Increment Modulo the Loop Count See Note a. See Note a. See Note a. See Short Form Direct 2. Direct Register The second method is a direct addressing method. The address of the RAM is directly specified by the address field of the instruction. Because this addressing method consumes nine bits (0-511) of the instruction field, some instructions cannot use this mode (Figure 6). Figures 8 to 13 show the different register instruction formats along with the two tables below Figure 8. b D8 n3 S3 n2 S2 n1 D3 n0 D2 RAM Address RAM Bank Note: a. If bit 8 is zero, P0:0 to P2:0 are selected; if bit 8 is one, P0:1 to P2:1 are selected. When Loop mode is selected, the pointer to which the loop is referring will cycle up or down, depending on whether a -LOOP or +LOOP is specified. The size of the loop is obtained from the least significant three bits of the Status Register. The increment or decrement of the register is accomplished modulo the loop size. As an example, if the loop size is specified as 32 by entering the value 101 into bits 2-0 of the Status Register (S2-S0) and an increment +LOOP is specified in the address field of the instruction, i.e., the RPi field is 11xx, then the register specified by RPi will increment, but only the least significant five bits will be affected. This means the actual value of the pointer will cycle round in a length 32 loop, and the lowest or highest value of the loop, depending on whether the loop is up or down, is set by the three most significant bits. This allows repeated access to a set of data in RAM without software intervention. To clarify, if the pointer value is 10101001 and if the LOOP = 32, the pointer increments up to 10111111, then drops down to 10100000 and starts again. The upper three bits remaining unchanged. Note that the original value of the pointer is not retained. Figure 7. Short Form Direct Address 3. Short Form Direct Dn:b n = 0-3, b = 0-1 The last method is called Short Form Direct Addressing, where one out of 32 addresses in internal RAM can be specified. The 32 addresses are the 16 lower addresses in RAM Bank 0 and the 16 lower addresses in RAM Bank 1. Bit 8 of the instruction field determines RAM Bank 0 or 1. The 16 addresses are determined by a 4-bit code comprised of bits S3 and S4 of the status register and the third and fourth bits of the Source/ Destination field. Because this mode can specify a direct address in a short form, all of the instructions using the register indirect mode can use this mode (Figure 7). This method can access only the lower 16 addresses in the both RAM banks and as such has limited use. The main purpose is to specify a data register, located in the RAM bank, which can then be used to point to a program memory location. This facilitates down-loading look-up tables, etc. from program memory to RAM. D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 RAM Address Opcode Figure 6. Direct Internal RAM Address Format 10 DC 4083-00 ZILOG PRELIMINARY Z89C00 16-BIT DIGITAL SIGNAL PROCESSOR INSTRUCTION FORMAT D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Source field Destination field RAM Bank selection Opcode Note: Source/Destination fields can specify either register or RAM addresses in RAM pointer indirect mode. Figure 8. General Instruction Format A. Registers Source/Destination 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Register BUS** X Y A SR STACK PC P** EXT0 EXT1 EXT2 EXT3 EXT4 EXT5 EXT6 EXT7 B. Register Pointers Field Source/Destination 00xx 01xx 10xx 11xx xx00 xx01 xx10 xx11 Meaning NOP +1 -1/LOOP +1/LOOP P0:0 or P0:1* P1:0 or P1:1* P2:0 or P2:1* Short Form Direct Mode Notes: * If RAM Bank bit is 0, then Pn:0 are selected. If RAM Bank bit is 1, then Pn:1 are selected. ** Read only. D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Short Immediate Data 000 001 010 011 100 101 110 111 Reg. Pointer P0:0 P1:0 P2:0 NA P0:1 P1:1 P2:1 NA Opcode 00011 Figure 9. Short Immediate Data Load Format DC 4083-00 11 ZILOG PRELIMINARY Z89C00 16-BIT DIGITAL SIGNAL PROCESSOR INSTRUCTION FORMAT (Continued) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1st Word General Instruction Format D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 2nd Word Immediate Data Figure 10. Immediate Data Load Format D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ACC Modification Codes 0 0 0 0 ROR Rotate right 0 0 0 1 ROL Rotate left 0 0 1 0 SHR Shift right 0 0 1 1 SHL Shift left 0 1 0 0 INC Increment (LSB) 0 1 0 1 DEC Decrement (LSB) 0 1 1 0 NEG Negate 0 1 1 1 ABS Absolute Condition Codes 0 0 0 0 TRUE 0 0 0 1 ---0 0 1 0 U01=0 0 0 1 1 UO1=0 0 1 0 0 C =0 0 1 0 1 Z=0 0 1 1 0 OV=0 0 1 1 1 N=0 1xxx ---0 0 0 0 TRUE 0001 ---0 0 1 0 UO0=1 0 0 1 1 UO1=1 0 1 0 0 C=1 0 1 0 1 Z=1 0 1 1 0 OV=1 0 1 1 1 N=1 1xxx ---0 = Negative Condition 1 = Positive Condition Opcode 1001000 Figure 11. Accumulator Modification Format 12 DC 4083-00 ZILOG PRELIMINARY Z89C00 16-BIT DIGITAL SIGNAL PROCESSOR D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1st Word xxxx Condition Codes 0 0 0 0 TRUE 0 0 0 1 ---0 0 1 0 UO0=0 0 0 1 1 UO1=0 0 1 0 0 C=0 0 1 0 1 Z=0 0 1 1 0 OV=0 0 1 1 1 N=0 1xxx ---0 0 0 0 TRUE 0001 ---0 0 1 0 UO0=1 0 0 1 1 UO1=1 0 1 0 0 C=1 0 1 0 1 Z=1 0 1 1 0 OV=1 0 1 1 1 N=1 1xxx ---Condition 0 = Negative Condition 1 = Positive Condition Opcode 0100110 Branch 0 1 0 0 1 0 0 Call D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 2nd Word Branch Address Figure 12. Branching Format D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 xx10 xx11 x1x0 x1x1 1xx0 1xx1 xxxx Reset C flag Set C flag Reset IE Flag (Interrupt enable) Set IE Flag Reset OP Flag (Overflow protection) Set OP Flag Opcode 1 0 0 1 0 1 0 Mod Figure 13. Flag Modification Format DC 4083-00 13 ZILOG PRELIMINARY Z89C00 16-BIT DIGITAL SIGNAL PROCESSOR ADDRESSING MODES This section discusses the syntax of the addressing modes supported by the DSP assembler. The symbolic name is Symbolic Name X,Y,PC,SR,P EXTn,A,BUS @A Hardware Registers Accumulator Memory Indirect Direct Address Expression Long (16-bit) Immediate Value Short (8-bit) Immediate Value Pointer Register Indirect Pointer Register Indirect with Increment Pointer Register Indirect with Loop Decrement Pointer register Indirect with Loop Increment Pointer Register Memory Indirect Data Register Memory Indirect Pointer Register Memory Indirect with Loop Decrement Pointer Register Memory Indirect with Loop Increment Pointer Register Memory Indirect with Increment There are eight distinct addressing modes for transfer of data (Figure 4 and the table above). pointer. The "@" symbol indicates "indirect" and precedes the pointer, so @P1:1 tells the processor to read or write to a location in RAM1, which is specified by the value in the pointer. 14 DC 4083-00 ZILOG PRELIMINARY Z89C00 16-BIT DIGITAL SIGNAL PROCESSOR CONDITION CODES The following table defines the condition codes supported by the DSP assembler. If the instruction description refers to the Name NU1 NZ OV PL U0 U1 UGE ULT Z Description Not User One Not zero Overflow Plus (Positive) User Zero User One Unsigned Greater Than or Equal (Same as NC) Unsigned Less Than (Same as C) Zero DC 4083-00 15 ZILOG PRELIMINARY Z89C00 16-BIT DIGITAL SIGNAL PROCESSOR INSTRUCTION DESCRIPTIONS Inst. ABS ADD Description Absolute Value Addition Synopsis ABS[ AND Bitwise AND AND CALL CCF CIEF COPF CP Subroutine call Clear carry flag Clear Carry Flag Clear OP flag Comparison CALL [ DEC INC JP Decrement Increment Jump DEC [ 16 DC 4083-00 ZILOG Inst. LD Description Load destination with source Synopsis LD PRELIMINARY Operands A, Z89C00 16-BIT DIGITAL SIGNAL PROCESSOR Words Cycles Examples 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 3 1 1 1 1 1 1 1 1 1 2 3 3 1 1 LD A,X LD A,D0:0 LD A,P0:1 LD A,@P1:1 LD A,@D0:0 LD A,124 LD 124,A LD D0:0,EXT7 LD P1:1,#%FA LD P1:1,EXT1 LD@P1:1,#1234 LD @P1:1+,X LD Y,P0:0 LD SR,D0:0 LD PC,#%1234 LD X,@A LD Y,@D0:0 LD A,@P0:0-LOOP LD X,EXT6 Note: If X or Y register is the destination, an automatic multiply operation is performed. Note: The P register is Read Only and cannot be destination. Note: LD EXTN, EXTN is not allowed. Note: LD A, @A is not allowed. MLD Multiply MLD Note: If src1 is Note: If src1 is DC 4083-00 17 ZILOG PRELIMINARY Z89C00 16-BIT DIGITAL SIGNAL PROCESSOR INSTRUCTION DESCRIPTIONS (Continued) Inst. Description Synopsis Operands Words Cycles 1 1 1 1 1 1 1 1 Examples MPYS Multiply and subtract MPYS MPYS A,@P0:0 MPYS A,@P1:0,OFF MPYS @P1:1,@P2:0 MPYS @P0:1,@P1:0,ON Note: If src1 is POP Pop value from stack POP PUSH Push value onto stack PUSH RET RL RR Return from subroutine Rotate Left Rotate Right RET RL 18 DC 4083-00 ZILOG Inst. SCF SIEF SLL Description Set C flag Set IE flag Shift left logical Synopsis SCF SIEF SLL SOPF SRA PRELIMINARY Operands None None [ Z89C00 16-BIT DIGITAL SIGNAL PROCESSOR Words Cycles 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 2 3 1 1 1 1 1 2 3 1 1 1 Examples SCF SIEF SLL NZ,A SLL A SOPF SRA NZ,A SRA A SUB A,P1:1 SUB A,D0:1 SUB A,#%2C2C SUB A,@D0:1 SUB A,%15 SUB A,@P2:0-LOOP SUB A,STACK XOR A,P2:0 XOR A,D0:1 XOR A,#13933 XOR A,@@P2:1+ XOR A,%2F XOR A,@P2:0 XOR A,BUS SOPF Set OP flag SRA SUB Shift right arithmetic Subtract XOR Bitwise exclusive OR XOR Bank Switch Enumerations. The third (optional) operand of the MLD, MPYA and MPYS instructions represents whether a bank switch is set on or off. To more clearly represent this, two keywords are used (ON and OFF) which state the direction of the switch. These keywords are referred to in the instruction descriptions through the DC 4083-00 19 ZILOG PRELIMINARY Z89C00 16-BIT DIGITAL SIGNAL PROCESSOR ABSOLUTE MAXIMUM RATINGS Symbol VCC TSTG TA Description Supply Voltage(*) Storage Temp. Oper. Ambient Temp. Min -0.5 -65 Max 7.0 +150 Units V C C Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended period may affect device reliability. Notes: * Voltages on all pins with respect to ground. See Ordering Information STANDARD TEST CONDITIONS The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to ground. Positive current flows into the referenced pin (Test Load Diagram, Figure 14). From Output Under Test +5V 2.1 K 150 pF 9.1 K Figure 14. Test Load Diagram DC ELECTRICAL CHARACTERISTICS (VCC = 5V 5%, TA = 0C to +70C unless otherwise specified) Symbol ICC ICC1 VIH VIL IIL VOH VOL IFL Parameter Supply Current Halt Mode Input High Level Input Low Level Input Leakage Output High Voltage Output Low Voltage Output Floating Leakage Current IOH = -100 A IOL = 0.5 mA Condition VCC = 5.25V fclock = 10 MHz VCC = 5.25V fclock = 0 MHz (stopped) Min. Max. 60 1 0.9 VCC 0.1 VCC 1 VCC - 0.2 0.5 5 5 Units mA mA V V A V V A 20 DC 4083-00 ZILOG PRELIMINARY Z89C00 16-BIT DIGITAL SIGNAL PROCESSOR AC ELECTRICAL CHARACTERISTICS (VCC = 5V 5%, TA = 0C to +70C unless otherwise specified) No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Symbol TCY PWW Tr Tf TEAD TXVD TXWH TXRS TXRH TIEDR TIEDF TINS TINL TPAD TPDS TPDH TCTLS TCTLH RDYS RDYH Parameter Clock Cycle Time Clock Pulse Width Clock Rise Time Clock Fall Time EA,ER//W Delay from CK EXT Data Output Valid from CLK EXT Data Output Hold from CLK EXT Data Input Setup Time EXT Data Input Hold from CLK /EI Delay Time from Rising CLK Edge /EI Delay Time from Falling CLK Edge Interrupt Setup Time Interrupt Hold Time PA Delay from CLK PD Input Setup Time PD Input Hold Time Halt Setup Time Halt Hold Time Ready Setup Time Ready Hold Time Min. 100 45 2 2 9 5 6 15 5 3 0 5 15 5 20 20 5 20 10 7 Max. 1000 4 4 33 27 22 15 15 23 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 22 28 DC 4083-00 21 ZILOG PRELIMINARY Z89C00 16-BIT DIGITAL SIGNAL PROCESSOR AC TIMING DIAGRAM 1 2 7 CLK 6 5 11 10 /EI 5 ER//W EXT Bus: Output EXT15-EXT0 Valid Data Out EA2-EA0 Valid Address Out 5 /RDYE Figure 15. Write To External Device Timing 22 DC 4083-00 ZILOG PRELIMINARY Z89C00 16-BIT DIGITAL SIGNAL PROCESSOR 1 2 9 CLK 8 5 16 10 /EI ER//W EXT Bus: Input EXT15-EXT0 Valid Data In EA2-EA0 Valid Address Out 5 /RDYE Figure 16. Read From External Device Timing DC 4083-00 23 ZILOG PRELIMINARY Z89C00 16-BIT DIGITAL SIGNAL PROCESSOR AC TIMING DIAGRAM 1 2 7 CLK 6 5 11 10 /EI 5 ER//W EXT Bus: Output EXT15-EXT0 Valid Data Out EA2-EA0 Valid Address Out /RDYE 19 20 Figure 17. Write To External Device Timing (/RDYE used to hold data one clock cycle)* Note: * /RDYE is checked during rising edge of clock. 24 DC 4083-00 ZILOG 1 2 PRELIMINARY 9 8 Z89C00 16-BIT DIGITAL SIGNAL PROCESSOR CLK 5 11 10 /EI 5 ER//W EXT Bus: Input EXT15-EXT0 Valid Data In EA2-EA0 Valid Address Out /RDYE 19 20 Figure 18. Read From External Device Timing (/RDYE used to hold data one clock cycle)* Note: * /RDYE is checked during rising edge of clock. DC 4083-00 25 ZILOG PRELIMINARY Z89C00 16-BIT DIGITAL SIGNAL PROCESSOR AC TIMING DIAGRAM 1 2 15 CLK 14 14 PA15-PA0 16 PD15-PD0 17 18 HALT Figure 19. Memory Port Timing 1 2 CLK 12 INT2-INT0 13 18 HALT 17 Figure 20. Interrupt and HALT Timing 26 DC 4083-00 ZILOG PRELIMINARY Z89C00 16-BIT DIGITAL SIGNAL PROCESSOR PACKAGE INFORMATION 68-Pin PLCC Package Diagram DC 4083-00 27 ZILOG PRELIMINARY Z89C00 16-BIT DIGITAL SIGNAL PROCESSOR ORDERING INFORMATION Z89C00 10 MHz 68-pin PLCC Z89C0010VSC 15 MHz 68-pin PLCC Z89C0015VSC For fast results, contact your local Zilog sales office for assistance in ordering the part desired. Package V = Plastic Leaded Chip Carrier Temperature S = 0C to +70C Speeds 10 = 10 MHz 15 = 15 MHz Environmental C = Plastic Standard Example: Z 89C00 10 V S C is a Z89C00, 10 MHz, PLCC, 0C to +70C, Plastic Standard Flow Environmental Flow T emperature Package Speed Product Number Zilog Prefix (c) 1997 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document. Zilog's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 Telex 910-338-7621 FAX 408 370-8056 Internet: http://www.zilog.com 28 DC 4083-00 |
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